The present invention relates to systems with multiple processing devices and, more particularly, to memory coherency in such systems.
Information processing systems have evolved to the point of requiring many tightly coupled processors. Each processor can be viewed as a separate system which is coupled by a global bus or interconnect structure. In such systems, each processor system typically has a main memory device and one or more separate cache memories. As such systems evolved, the preferred implementation is to have a fully coherent memory system. For example, cache coherency is expected when programming pursuant to Unix-style multi-processor software conventions. A disadvantage with fully coherent memory systems is the expense and delay associated with the additional processing required to maintain such systems fully coherent. As the number of processors increases in a system, the degree of complexity in ensuring coherency also increases. An example of a multiprocessor computer system which utilizes cache coherency management protocols is taught in U.S. Pat. No. 5,303,362. The requirement to maintain coherency throughout the system imposes a requirement to broadcast all coherence traffic and that imposes an undesirable load on the global interconnect and uninterested processing elements.
In yet other systems, software is used to make devices having memory which is inherently incoherent to be coherent with other memory in the system. Performance is often degraded as time is required for a software routine to identify and retrieve a most current piece of data. The software execution associated with identifying and resolving memory coherency issues also increases system overhead and slows operational speed.
In multi-processing systems using a variety of processing elements, the entire system has previously been viewed as a single entity from a memory coherency standpoint. Therefore, cache coherency issues affect each and every processing element of known systems. For the reasons above and the continued demand to interconnect more and more processing devices, a more efficient memory coherency methodology is desired.